1. Field of the Invention
The present invention relates generally to the power supply circuitry of battery powered devices in which low power consumption is critical.
2. Related Art
In many battery powered devices there exists a power saving mode that a device may enter in order to save power and extend battery life. This is especially important in devices such as cellular phones. In order to maximize battery life, the devices must have very low power consumption. At the same time, the devices must quickly respond to input from a user.
DC-DC converters are a part of a larger power supply circuitry. The latest DC-DC Converters drain about 15 uA from the battery while operating in the power save or “No Load Current” mode. This power save mode is also referred to as Pulse Frequency Modulation (“PFM”) mode or pulse skipping mode, whereas the device would otherwise be in operating mode, which employs Pulse Width Modulation (“PWM”). In the power save mode of many current devices, low or quiescent current usage is achievable by turning off all of the building blocks except the reference voltage and two comparators when the converter is skipping pulses.
In the operating mode, the DC-DC converter must regulate the output voltage at high load current. While in the operating mode the device operates at a fixed switching frequency and the regulation is achieved using error loop feedback. The recovery time to a high load current of the operating mode from the low current power save mode depends on the error loop setting time from the power save state and on the slew rate of the error amplifier.
FIG. 1 shows the block diagram of a prior art current-mode step-down DC-DC converter.
The PFM circuitry 138 resets the latch 106 during power save mode. In PWM mode the latch is being reset by the error loop feedback from PWM circuitry 125 comprising error amp 126, comparator 132 and current sensing and slope compensation circuitry block 134. The error amp 126 produces a voltage VE and the current sensing and slope compensation circuitry block 134 produces a voltage Vs, both of which are inputs to comparator 132. Latch 106 drives transistors 110 and 112 via drivers 108. Inductor 114 is directly or indirectly coupled to the output of transistors 110 and 112 and to a Voltage output 116.
The PFM circuitry 138 resets the latch during the power save (or Pulse Skipping) mode. In PWM mode the latch is being reset by the error loop feedback of PWM circuitry 125. The converter switches automatically between the two modes of operation. The switching is accomplished by the ‘OR’ gate 136 in FIG. 1.
In PWM circuitry 125, the output voltage level VE of error amp 126 changes with the load current and input voltage. The ‘Current sensing and Slope Compensation’ block 134 provides a voltage ramp proportional to the inductor current. The comparator 132 compares the voltage ramp (Vs) to the error signal (VE) and resets the flip-flop.
In the PWM mode operation, the converter 100 operates at a fixed frequency while controlling the duty cycle of transistor 110. At the beginning of each clock cycle, transistor 110, which is preferably but not necessarily a P-channel type transistor, is turned on. The current in inductor 114 ramps up and is sensed via the Current Sensing and Slope Compensation circuitry block 134. Transistor 110 is turned off when the sensed current causes the PWM comparator 132 to trip (as seen in the little graph in FIG. 1). After a minimum dead time preventing shoot through current, transistor 112, which is preferably but not necessarily an N-channel type transistor, will be turned on and the inductor current ramps down. As the clock cycle is completed, transistor 112 will be turned off and the next clock cycle starts.
While in power saving or pulse skipping mode, the PWM circuitry 125 including error amplifier 126 is turned off to save power and its output voltage is zero. When a high current load transition takes place the error amplifier is turned on and its output voltage rises to the regulation level. The converter 100 runs with a low duty cycle until the output voltage 116 regulation level is reached and the recovery time is a function of the error amplifier 126 slew rate. Because the recovery time depends on the slew rate in these prior devices, the recovery takes a relatively long time. In the prior art example shown in FIG. 1, the recovery time is on the order of 50 to 70 microseconds or longer. This recovery time is significant and is an undesirable quality of prior converters.